Research on Synchronous Sampling Clock Jitter of Power System

The principle of synchronous sampling is introduced and the sampling noise brought by clock jitter is analyzed in this paper. The method of calculating the SNR of sampling signal interfered by clock jitter is proposed and the condition that clock jitter noise can be neglected is derived too. This paper proposes a kind of equal phase mean filter fitting for clock jitter noise. The effects of this filter with different amount of points are compared. The simulation result shows that equal phase mean filtering can attenuate clock jitter noise effectively.