Title :
CoSi/sub 2/ with low diode leakage and low sheet resistance at 0.065 /spl mu/m gate length
Author :
Hong, Q.Z. ; Shiau, W.T. ; Yang, H. ; Kittl, J.A. ; Chao, C.P. ; Tsai, H.L. ; Krishnan, S. ; Chen, I.C. ; Havemann, R.H.
Author_Institution :
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
This paper presents a comprehensive study of four diode leakage reduction methods, i.e. pre-metal deposition sputter clean, pre-metal deposition amorphization implant, high temperature silicidation, and high temperature metal deposition, for Co salicided junctions and their impact on sub-0.18 /spl mu/m CMOS device performance. The preferred methods are high temperature silicidation and/or high temperature Co deposition, which result in low diode leakage and little device degradation. CoSi/sub 2/ formed by the low diode leakage processes can achieve a mean sheet resistance of /spl sim/6 ohm/sq. on N+ gates with gate lengths down to 0.065 /spl mu/m.
Keywords :
MOSFET; cobalt compounds; ion implantation; leakage currents; semiconductor device reliability; surface cleaning; 0.065 to 0.18 micron; CMOS device performance; CoSi/sub 2/; device degradation; diode leakage; gate length; high temperature metal deposition; high temperature silicidation; mean sheet resistance; pre-metal deposition amorphization implant; pre-metal deposition sputter clean; sheet resistance; Argon; Degradation; Implants; Plasma temperature; Semiconductor diodes; Silicidation; Surface cleaning; Surface contamination; Temperature distribution; Tin;
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-4100-7
DOI :
10.1109/IEDM.1997.649475
