Signal adaptive hardware implementation of a smart system for time-frequency signal analysis

This paper outlines the development of an efficient multi-cycle, signal adaptive hardware design of a system for time-frequency (TF) signal analysis, suitable for real-time implementation on an integrated chip. The proposed design allows the implemented system to take variable number of clock (CLK) cycles (the only necessary ones regarding the high auto-terms quality) in different TF points within the execution. In this way, the proposed design optimizes execution time of the implemented system, producing a pure cross-terms-free Wigner distribution (WD) signal representation. Additionally, the proposed multi-cycle design optimizes both critical design performances, related to the complexity of the hardware, and the CLK cycle time. The design has been verified by a field-programmable gate array (FPGA) circuit design, suitable of performing processing of nonstationary signals in real-time.