Vertical NPN bipolar junction transistors fabricated in silicon-on-sapphire

Author

Cartagena, E.N. ; Offord, B.W. ; Walker, H.

Author_Institution

US Naval Ocean Syst. Center, San Diego, CA, USA

fYear

1991

fDate

1-3 Oct 1991

Firstpage

122

Lastpage

123

Abstract

Vertical NPN bipolar junction transistors were fabricated on DSPE (double solid-phase epitaxy) improved SOS (silicon-on-sapphire) using conventional furnace anneals. Transistors with an effective emitter area of 40 square microns were measured for current gain (β_DC) and Early voltage (V_A). Functional devices with β_DC values of up to 70, V _A values of 40 volts, and f_T values of 1 gigahertz were recorded. A thin SOS film (0.27 micron) was regrown with DSPE process to reduce the microtwin defect concentration. A common emitter characteristic curve for a BJT (bipolar junction transistor) fabricated in DSPE improved SOS is shown. It can be seen from this sample that the effects of enhanced diffusion along dislocations causing emitter-collector shorts are minimized by utilizing the DSPE process prior to epitaxy deposition

Keywords

bipolar transistors; semiconductor epitaxial layers; semiconductor technology; semiconductor-insulator boundaries; solid phase epitaxial growth; 40 V; DSPE; Early voltage; NPN transistors; SOS; Si-Al₂O₃; bipolar junction transistors; common emitter characteristic curve; current gain; double SPE; double solid-phase epitaxy; epitaxy deposition; f_T; furnace anneals; vertical bipolar transistors; Annealing; Epitaxial growth; Furnaces; Implants; Leakage current; Low voltage; Oceans; Silicon on insulator technology; Solid state circuits; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1991. Proceedings, 1991., IEEE International

Conference_Location

Vail Valley, CO

Print_ISBN

0-7803-0184-6

Type

conf

DOI

10.1109/SOI.1991.162887

Filename

162887