Timing driven RTL-to-RTL partitioner for multi-FPGA systems

This paper discusses a novel RTL to RTL partitioner flow to better cope with the challenges of modern rapid system prototyping on Multi-FPGA sytems. The proposed system partitioner flow is timing driven to evaluate the best achievable system performance within a given search space, reduces turn-around times if RTL code changes and enables more efficient debugging capabilities. System prototyping is often compared to emulation as alternative verification method, whereas system performance is used as one of the comparison points. This paper highlights some fundamental aspects for the achievable system performance of rapid system prototyping on Multi-FPGA systems.