A low-complexity implementation of QC-LDPC encoder in reconfigurable logic

Low Density Parity Check(LDPC) codes are a special class of error correction codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favorable structure. In this paper, a methodology for optimized hardware multiplication by constant matrices in GF(2) is introduced and then applied to the Quasi-Cyclic LDPC encoding algorithm. Taking advantage of the fact that the parity check matrix rarely changes, the signals in many cases are hard-wired into the LUTs and thus the cyclic-shifters and block-memories conventionally used are eliminated. Therefore, the proposed framework leads to less complex, mapped to reconfigurable logic designs, whereas it combines the performance of hard-wired solutions (high throughput, low latency) and the flexibility of the software and its hardware counterparts. These advantages in terms of hardware savings and throughput prove that the proposed encoder scheme is suitable for high-speed applications, such as long-haul optical transmission, where speed and resources utilization are a major issue.