Identifying sequences of optimizations for HW/SW compilation

This PhD work focuses on techniques to devise sequences of compiler optimizations able to increase the performance of a given function/program when mapped to software or to hardware. The techniques are being evaluated using an integrated hardware/software compiler controlled by strategies expressed in LARA, a domain-specific language specially developed to guide/control code instrumentation, code transformations and compiler optimizations. We started by evaluating a Design Space Exploration (DSE) scheme based on a Simulated Annealing approach expressed in LARA. This scheme is able to explore compilation design space points generated by distinct compilation sequences. In our first studies we apply compilation strategies to two hot-spot functions from two industrial applications provided in the context of the REFLECT project, Grid Iterate, from a 3-D Path Planning application, and Filter Subband, part of an MPEG audio encoder. A first evaluation of the DSE scheme resulted in speed-ups of 1.75 and 1.23 for Filter Subband, and 2.24 and 1.13 for Grid Iterate, when targeting a MicroBlaze processor and reconfigurable hardware, respectively.