Jitter in a wireless clock distribution system

Author

Dickson, Timothy ; Floyd, Brian ; O, Kenneth

Author_Institution

Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA

fYear

2002

fDate

2002

Firstpage

154

Lastpage

156

Abstract

The jitter of a transmitted wireless clock signal has been measured and found to behave much like jitter of conventionally distributed clock signals. Noise from nearby digital circuits can degrade receiver sensitivity by reducing LNA gain and shifting the divider self-oscillation frequency. This increases clock jitter and, in extreme conditions, can cause failure in the clock receiver circuits to lock on to the transmitted clock signal. The clock can be re-locked by increasing the transmitted power.

Keywords

CMOS integrated circuits; circuit noise; clocks; digital integrated circuits; integrated circuit interconnections; radio receivers; radio transmitters; timing jitter; CMOS foundry process; LNA gain; clock jitter; clock re-locking; clock receiver circuit lock on failure; clock transmitted power; digital circuit noise; divider self-oscillation frequency shift; jitter; receiver sensitivity; transmitted wireless clock signal; wireless clock distribution system; CMOS technology; Circuit noise; Clocks; Digital circuits; Frequency conversion; Inverters; Jitter; Noise generators; Receiving antennas; Semiconductor device noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International

Print_ISBN

0-7803-7216-6

Type

conf

DOI

10.1109/IITC.2002.1014917

Filename

1014917