Towards a RISC instruction set architecture for the 32-bit VLIW DSP processor core

Digital Signal Processors (DSPs), compared to general-purpose processors, have shown their great contribution to the implementation of digital signal processing algorithms such as digital filtering and Fourier analysis. This work deals with the RISC instruction set architecture (ISA) for the 32-bit VLIW Fixed-point DSP processor core proposed in our previous work. The designed DSP has been described in terms of groups of instructions, the opcode maps, and suggested design of the data path based on the proposed ISA. Moreover, advanced and enhanced instructions aimed at audio and image applications will also be presented in this work.