Title :
A Compact 12 bit NMOS Array Multiplier-Accumulator
Author :
Benschop, Nico ; Pfennings, Leo
Author_Institution :
Philips Research Laboratories, Eindhoven, The Netherlands.
Abstract :
A fast (200 ns) and low power (250 mw) 12 bit static NMOS multiplier-accumulator for signal processing is described. It contains a 12 × 12 bit parallel array multiplier (AB) and a 24 bit accumulator (Q), and computes Q Q±AB. The use of inverting full adder cells yields a very compact and efficient array of only 1.5 mm2.
Keywords :
Adders; Arithmetic; Array signal processing; Delay; Digital signal processing; Inverters; Logic arrays; Logic design; MOS devices; Pipelines;
Conference_Titel :
Solid State Circuits Conference, 1981. ESSCIRC '81. 7th European
Conference_Location :
Freiburg, F. R. Germany
