Title :
Low power digital circuit design
Author :
Sakurai, Takayasu
Author_Institution :
Inst. of Ind. Sci., Univ. of Tokyo, Japan
Abstract :
The paper describes approaches for achieving low power digital circuits. The approaches are classified from the standpoint of spatial granularity, temporal granularity and variable granularity. The trend is moving from coarse-grain to the finer grain to save more power with the higher engineering cost. The newer approach includes dynamic adaptive control of VDD and VTH at a block level. The paper also touches on low-power applications.
Keywords :
adaptive control; digital integrated circuits; integrated circuit design; low-power electronics; voltage control; dynamic adaptive voltage control; engineering cost; low power digital circuit design; low-power applications; spatial granularity; temporal granularity; threshold voltage; variable granularity; Adaptive control; Collaboration; Costs; Delay; Digital circuits; Dynamic voltage scaling; Energy consumption; Leakage current; Power engineering and energy; Threshold voltage;
Conference_Titel :
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European
Print_ISBN :
0-7803-8478-4
DOI :
10.1109/ESSDER.2004.1356476
