Title :
A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique
Author :
Yibin Ye ; Khellah, M. ; Somasekhar, D. ; Farhang, A. ; De, V.
Author_Institution :
Microprocessor Res., Intel Labs, Hillsboro, OR, USA
Abstract :
BLR is incorporated into a L1 cache design in a 100 nm dual-V/sub T/ technology to eliminate impacts of bitline leakage on performance and noise margin with minimal area overhead. Bitline delay is 23% better than the best conventional design, thus enabling 6 GHz operation at with 15% higher energy.
Keywords :
cache storage; 100 nm; 16 Kbyte; 6 GHz; L1 cache; area overhead; bitline delay; bitline leakage reduction technique; dual threshold voltage technology; noise margin; Cache storage; Clocks; Delay; Driver circuits; Energy storage; Frequency; Microprocessors; Random access memory; Stability; Voltage;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015042
