A novel method for forming gate spacer and its effects on the W/WNx/poly-Si gate stack

A novel method for forming the SiO₂/Si₃N₄ (O/N) gate spacer has been developed through applying a low temperature atomic layer deposition (ALD) SiO₂ film. Using this scheme, the Si-O rich interfacial dielectric layer formation and the metal (W) contamination caused by the selective oxidation (SO) process were controlled. Our technique also suppresses the thickness increase of the gate oxide during the SO and enhances the rounding of gate bird´s beak (GBB) at the gate edges. Furthermore, the O/N gate spacered device exhibits less junction leakage currents, about 1 order of magnitude lower gate induced drain leakage (GIDL) currents at the same V_t, and better hot carrier degradation (HCD) immunity compared to the N/O/N gated spacer device.