A 1.6 Gb/s, 3 mW CMOS receiver for optical communication

Author

Emami-Neyestanak, A. ; Liu, D. ; Keeler, G. ; Helman, N. ; Horowitz, M.

Author_Institution

Comput. Syst. Lab., Stanford Univ., CA, USA

fYear

2002

fDate

13-15 June 2002

Firstpage

84

Lastpage

87

Abstract

A 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-/spl mu/m CMOS process. This receiver has no transimpedance amplifier and uses the parasitic capacitor of the flip-chip bonded photodetector as an integrating element and resolves the data with a double-sampling technique. A simple feedback loop adjusts a bias current to the average optical signal, which essentially "AC couples" the input. The resulting receiver resolves an 11 /spl mu/A input, dissipates 3 mW of power, occupies 80 /spl mu/m/spl times/50 /spl mu/m of area and operates at over 1.6 Gb/s.

Keywords

CMOS integrated circuits; circuit feedback; digital communication; integrated optoelectronics; mixed analogue-digital integrated circuits; optical receivers; signal sampling; 0.25 micron; 1.6 Gbit/s; 11 muA; 3 mW; 50 micron; 80 micron; CMOS process; CMOS receiver; MQW detector; bias current; double-sampling technique; feedback loop; flip-chip bonded photodetector; optical communication; parasitic capacitor; Bonding; CMOS process; Capacitors; Feedback loop; Optical amplifiers; Optical design; Optical fiber communication; Optical receivers; Photodetectors; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015053

Filename

1015053