Title :
A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all
Author :
Ogawa, M. ; Ito, K. ; Shibata, T.
Author_Institution :
Dept. of Frontier Informatics, Univ. of Tokyo, Japan
Abstract :
A general-purpose vector-quantization (VQ) processor featuring high-speed and versatile winner search functions is presented. A new two-dimensionally bit-propagating scheme has been employed in the winner-take-all (WTA) circuit. As a result, the maximum/minimum value identification for 6 b 128 inputs in a single clock cycle has been accomplished, which is five times faster than the conventional approach (18 b comparison is carried out in three clock cycles). In addition, the new block addressing scheme developed in the present work enables various options in WTA operations. The chip was fabricated in a standard CMOS process and the operation was demonstrated by application to handwritten character recognition as an example.
Keywords :
CMOS digital integrated circuits; VLSI; character recognition equipment; digital signal processing chips; handwritten character recognition; search problems; vector quantisation; 2D bit-propagating scheme; CMOS process; VLSI chip; WTA circuit; block addressing scheme; data compression; general-purpose VQ processor; handwritten character recognition; high-speed winner search functions; maximum/minimum value identification; pattern recognition; vector-quantization processor; winner-take-all circuit; Application software; Character recognition; Circuits; Clocks; Data compression; Indium tin oxide; Informatics; Pattern recognition; Semiconductor device measurement; Vector quantization;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015095
