Title :
Novel Buried Bitline Integration for compact Cell Design in High-Performance embedded Flash Memory with Deep Trench Isolation
Author :
Tilke, A.T. ; Pescini, L. ; Stiftinger, M. ; Kakoschke, R. ; Shum, D. ; Chan, N. ; Kim, S.R. ; Han, K.J.
Author_Institution :
Infineon Technol. North America, San Jose, CA
Abstract :
In this work, we present a novel buried BL (BBL) concept that links the source contacts of each individual BL via the isolated p-well; thus effectively eliminating one metal line per BL and reducing overall cell size. In comparison to the UCPE cell, a conservative cell size shrink of about 40% can be achieved from a standard embedded 21F2 DT-UCPE-cell. The schematic cell layout is shown and comparison to that of a conventional UCP-layout is presented
Keywords :
embedded systems; flash memories; 21F2 DT-UCPE-cell; buried BL; buried bitline integration; cell size reduction; compact cell design; deep trench isolation; embedded flash memory; p-well isolation; uniform channel programming-erase operation; CMOS logic circuits; CMOS process; CMOS technology; Character generation; Contacts; Etching; Flash memory; Implants; Isolation technology; Silicides;
Conference_Titel :
Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st
Conference_Location :
Monterey, CA
Print_ISBN :
1-4244-0027-9
DOI :
10.1109/.2006.1629478
