DocumentCode :
190646
Title :
Optimal voltage signal sensing of NAND flash memmory for LDPC code
Author :
Shigui Qi ; Dan Feng ; Jingning Liu
Author_Institution :
Sch. of Comput., Huazhong Univ. of Sci. & Technol., Wuhan, China
fYear :
2014
fDate :
20-22 Oct. 2014
Firstpage :
1
Lastpage :
6
Abstract :
Low-density parity-check (LDPC) code can provide stronger error correcting performance in NAND flash memory. LDPC decoder requires accurate soft-decision log-likelihood ratio (LLR) information which demands fine-grained flash memory threshold voltage sensing operations. The threshold voltage sensing operations incur energy consumption and access latency penalty. Therefore, it is important to minimize the flash memory sensing operations without noticeable error correcting performance decreasing. We propose a new flash memory sensing strategy Ununiform-SOR (ununiform sensing in overlapping region) which can reduce 20% flash memory sensing operations than traditional non-uniform threshold voltage sensing without reducing the error correcting performance of LDPC code in NAND flash memory noise channel. The new Ununiform-SOR sensing strategy can reduce more than 20% reading energy consumption than the non-uniform sensing strategy. The abstract goes here.
Keywords :
decoding; energy consumption; error correction codes; flash memories; parity check codes; LDPC decoder; LLR; NAND flash memory; energy consumption; error correcting performance; latency penalty; low-density parity-check code; optimal voltage signal sensing; soft-decision log-likelihood ratio; threshold voltage sensing operations; Ash; Energy consumption; Entropy; Noise; Parity check codes; Sensors; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems (SiPS), 2014 IEEE Workshop on
Conference_Location :
Belfast
Type :
conf
DOI :
10.1109/SiPS.2014.6986077
Filename :
6986077
Link To Document :
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