DocumentCode
190695
Title
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy
Author
Palumbo, Francesca ; Sau, Carlo ; Raffo, Luigi
Author_Institution
PolComIng Dept., Univ. of Sassari, Alghero, Italy
fYear
2014
fDate
20-22 Oct. 2014
Firstpage
1
Lastpage
6
Abstract
Applications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are necessary to implement efficient multi-functional runtime reconfigurable signal processing platforms. In this work, we adopt dataflow specifications as a starting point to challenge power minimization.
Keywords
data flow computing; directed graphs; formal specification; power aware computing; reconfigurable architectures; resource allocation; video coding; coarse-grained reconfigurable design; dataflow based strategy; dataflow program; dataflow specification; directed graph; hardware complexity management; multifunctional runtime reconfigurable signal processing platform; power minimization; power-aware design framewor; power-awareness; reconfigurable video coding; resource-power balance; Decision support systems; Generators; Government; Pareto analysis; Power demand; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems (SiPS), 2014 IEEE Workshop on
Conference_Location
Belfast
Type
conf
DOI
10.1109/SiPS.2014.6986104
Filename
6986104
Link To Document