DocumentCode :
1907576
Title :
A new partitioning framework for uniform clock distribution during high-level synthesis
Author :
Krishnamurthy, H. ; Maaz, M.B. ; Bayoumi, M.A.
Author_Institution :
Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
Volume :
6
fYear :
1998
fDate :
31 May-3 Jun 1998
Firstpage :
381
Abstract :
This weighted cluster partitioning technique is aided by an innovative resource allocation technique which provides a uniform resource utilization. This results in a uniform power requirement distribution across the synthesized chip which is practically beneficial as well. The resource cluster information obtained from this new partitioning synthesis framework could be used to aid the hierarchical placement and routing tools as well as the clock-router to design and produce a close to optimal uniform clock routing. This new framework applies the idea of local (intra-cluster) communication, while minimizing global communication busses. This resulted in a low-power design as well. The partitioner cost function considers three factors: the number of clock lines per unit area, the number of cuts between clusters, and the size of partitions. Experimental results show that this partitioning framework provides uniform clock distribution among clusters as well as fairly uniform sized partitions
Keywords :
clocks; high level synthesis; integrated circuit layout; logic partitioning; network routing; resource allocation; clock lines; global communication busses; hierarchical placement; high-level synthesis; intra-cluster communication; low-power design; optimal uniform clock routing; partition size; partitioning framework; resource allocation technique; uniform clock distribution; uniform power requirement distribution; uniform resource utilization; weighted cluster partitioning; Clocks; Cost function; Distributed computing; Flow graphs; Global communication; Hardware; High level synthesis; Logic; Resource management; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
Type :
conf
DOI :
10.1109/ISCAS.1998.705290
Filename :
705290
Link To Document :
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