Timing distribution in an on board processing communication system

This paper describes a timing distribution and a synchronisation scheme for a communication system with data regeneration and switching on board the satellite. The proposed concept is applied to a bit-synchronous system where the reference clock is generated on-board from an incoming very stable ground source. An auxiliary ground reference is operating in pre-aligned hot stand by mode, allowing an immediate hand over in case of interruption of the link to the primary reference. Clock quality in terms of phase jitter is evaluated throughout the system and is shown to impose negligible penalty on system performance. The synchronisation scheme has been simulated and successfully demonstrated by means of a laboratory model. The concept described in this paper is applied in the ESA on board processing system currently under development, but as such can be applied to any satellite system with on board regeneration and/or switching