Modeling, extraction and simulation of CMOS I/O circuits under ESD stress

Author

Li, Tong ; Tsai, Ching-Han ; Rosenbaum, Elyse ; Kang, Sung-Mo

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

Volume

6

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

389

Abstract

A CAD tool set for VLSI CMOS I/O circuit design is developed. It includes a circuit simulator, a layout extractor and a substrate resistance solver. This paper presents a new layout extractor for CMOS I/O circuits and a new method for modeling the substrate resistance. With these tools, for the first time, full I/O circuits can be simulated accurately at the circuit-level with the substrate-coupling effects taken into consideration. The CAD tools are demonstratively applied to an industrial circuit

Keywords

CMOS integrated circuits; VLSI; circuit analysis computing; circuit layout CAD; electrostatic discharge; equivalent circuits; integrated circuit layout; integrated circuit modelling; integrated circuit reliability; CAD tool set; CMOS I/O circuits; ESD stress; VLSI circuit design; circuit simulator; circuit-level simulation; layout extractor; substrate resistance modelling; substrate-coupling effects; Circuit simulation; Circuit testing; Computational modeling; Design automation; Electrostatic discharge; Protection; Semiconductor device modeling; Stress; Substrates; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.705292

Filename

705292