Reconfigurable computing for RC6 cryptography

This work presents an emerging reconfigurable hardware that potentially delivers flexible high performance for cryptographic algorithms. MorphoSys, a dynamic reconfigurable architecture that sustains implementations that can yield into equally or even better performance results than custom-hardware and yet preserves all the flexibility of general-purpose processors. With today´s great demand for secure communications systems, networks and the Internet, there is a growing demand for real-time implementation of cryptographic algorithms. As a case study, this paper presents the mapping and performance analysis for one of the five AES finalists cryptographic algorithms, namely RC6. Being an important and secure cryptographic algorithm, RC6 is considered well chosen to be mapped in order to test and evaluate the suitability of dynamic reconfigurable computer (RC) systems such as MorphoSys.