Title :
A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection
Author :
Tomiye, H. ; Terano, T. ; Nomoto, K. ; Kobayashi, T.
Author_Institution :
Sony Corp. Semicond. Network Co., Kanagawa, Japan
Abstract :
We have proposed a novel 2-bit/cell MONOS memory structure that features a wrapped gate. Programming and erasing are by source-side hot-electron injection and hot-hole injection, respectively. With this device, programming speeds <1 /spl mu/s with a programming current <2 /spl mu/A//spl mu/m, and erasing speeds <10 /spl mu/s have been achieved.
Keywords :
MIS devices; PLD programming; hot carriers; microprogramming; semiconductor device measurement; semiconductor storage; 1 mus; 10 mus; 2 bit; MONOS memory device; SiO/sub 2/-Si/sub 3/N/sub 4/-SiO/sub 2/; erasing speeds; hot-hole injection; memory erasing; memory programming; programming current; programming speeds; source-side hot-electron injection; wrapped-control-gate structure; Channel hot electron injection; Electronic mail; Energy consumption; Flash memory; Hot carriers; MONOS devices; Nonvolatile memory; Scalability; Secondary generated hot electron injection; Split gate flash memory cells;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015454
