Impact of die-to-die thermal coupling on the electrical characteristics of 3D stacked SRAM cache

We study the thermal coupling in a 3D stack with multiple cores in one tier and an SRAM array (cache) in a second tier with face-to-back bonding. For identical statistical distribution of power dissipation in cores, the SRAM sub-arrays experience much higher mean and variance in temperature in a 3D stack compared to a conventional 2D system. The increased variability in temperature increases leakage, degrades performance, and accelerates aging in 3D integrated SRAM. This is studied using 32nm predictive technology. Further, the spatial and temporal variations in performance of SRAM blocks become a strong function of the power variations in cores.