Title :
Test cost reduction by at-speed BISR for embedded DRAMs
Author :
Nagura, Yoshihiro ; Mullins, Michael ; Sauvageau, Anthony ; Fujiwara, Yoshinori ; Furue, K. ; Ohmura, Ryuji ; Komoike, Tatsunori ; Okitaka, Takenori ; Tanizaki, Tetsushi ; Dosaka, Katsumi ; Arimito, Kazutami ; Koda, Yukiyoshi ; Tada, Tetsuo
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
Abstract :
The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SoC) device test. This paper proposes putting the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7 mm2, about 2% of conventional SoC devices. Using an error storage table form contributes to realizing a small area penalty of the repair analysis function. e-DRAM functional test time was reduced about 20% less than the conventional method at wafer level testing. Moreover, the results of e-DRAM test and repair analysis using BISR is almost coincident with the conventional method
Keywords :
VLSI; application specific integrated circuits; automatic testing; high-speed integrated circuits; integrated circuit reliability; integrated circuit testing; integrated memory circuits; production testing; random-access storage; 166 MHz; SoC device test; at-speed BISR; automatic test equipment; built in self repair; embedded DRAMs; embedded memory; error storage table form; functional test time reduction; low cost ATE; onchip repair analysis function; system-on-chip device test; test cost reduction; wafer level testing; Algorithm design and analysis; Circuit testing; Clocks; Costs; Electronic equipment testing; Frequency; Information analysis; Random access memory; System testing; Test equipment;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966632
