A 0.25μm Fully Planarized CMOS Technology

Author

ter Beek, M. ; Nunan, P. ; Crank, S. ; Ta, L. ; Booth, R. ; Venkataraman, K.

Author_Institution

SEMATECH, Austin, TX, USA

fYear

1993

fDate

13-16 Sept. 1993

Firstpage

261

Lastpage

264

Abstract

CMOS devices with 0.25μm physical gate lengths were fabricated on 200mm wafers utilizing a twin well, double level metal, fully planarized process. Single work function n⁺ poly silicon was chosen as the gate electrode for its ease of manufacturability. Deep UV lithography was used to define the critical layers; Poly, Contacts, Metal 1, Vias and Metal 2. All other levels were exposed using i-line lithography. It was necessary to utilize fully planarized CMP dielectrics due to reduced depth of focus inherent in DUV lithography. Due to reliability considerations 2.5V was the targeted power supply voltage. Electrical and process data is presented.

Keywords

CMOS integrated circuits; chemical mechanical polishing; ultraviolet lithography; CMOS devices; DUV lithography; contact layer; deep UV lithography; double-level metal; fully-planarized CMOS technology; gate electrode; i-line lithography; metal-1 layer; metal-2 layer; physical gate lengths; planarized CMP dielectrics; polylayer; reliability considerations; single-work function polysilicon; size 0.25 mum; size 200 mm; twin well; vias layer; CMOS process; CMOS technology; Contacts; Dielectrics; Electrodes; Lithography; Manufacturing; Power supplies; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Conference_Location

Grenoble

Print_ISBN

2863321358

Type

conf

Filename

5435502