Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement

Extreme-voltage screening has been successfully implemented to enhance gate-oxide reliability of digital CMOS ICs. However, the success has not yet been extended to its analog counterparts. As a result, almost all the manufacturers employ the digital circuit screening process for the analog modules in mixed-signal CMOS ICs. Our pervious study had addressed the issues on how to properly stress analog circuits to enhance the gate-oxide reliability of mixed-signal CMOS integrated circuits, and the trade-off between the stress coverage and stress time. This paper presents two algorithms that generate a set of stress vectors for an analog circuit (1) to meet the stress coverage requirement and to result in a minimum stress time; and (2) to meet the stress time requirement and to result in a maximum stress coverage