A simple via duplication tool for yield enhancement

Author

Harrison, Neil

Author_Institution

Philips Semicond., Albuquerque, NM, USA

fYear

2001

fDate

2001

Firstpage

39

Lastpage

47

Abstract

Defect limited product yields are known to have a significant contribution from resistive or open vias between metal interconnect layers. A simple tool for via duplication is presented with application results. The tool automates the addition of redundant vias to existing customer product layouts where permitted by the design rules. Significant yield benefits are obtained when the technique is applied to a real product as part of a Design for Manufacturability (DfM) exercise. The potential for improved process robustness and enhanced fault tolerance is also demonstrated. Implications for yield modeling including critical areas and the relation of random defects to gross defects are discussed

Keywords

design for manufacture; fault tolerance; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated circuit yield; customer product layouts; defect limited product yields; design for manufacturability; design rules; enhanced fault tolerance; gross defects; integrated circuit layout element; metal interconnect layers; open vias; process robustness; random defects; resistive vias; via duplication tool; yield enhancement; yield modeling; Circuit faults; Design for manufacture; Electrical capacitance tomography; Failure analysis; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit technology; Integrated circuit yield; Manufacturing; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

Conference_Location

San Francisco, CA

ISSN

1550-5774

Print_ISBN

0-7695-1203-8

Type

conf

DOI

10.1109/DFTVS.2001.966750

Filename

966750