Clock Manipulation for Heterogeneous Emulation Environment

This paper presents an approach how to build an environment for simulation speedup in hardware. This is based on assumptions that a system specification, described in a hardware description language can be partitioned in a way that styles corresponding to different abstraction levels could be modeled using different simulators/emulators. The work in progress is described, where the main objective is to extend emulation environment such that the entire model of a system can be implemented on FPGA. Potential synchronization challenges are outlined and a solution for clock manipulation is proposed