Development of the special software tools for the defect/fault analysis in the complex gates from standard cell library

Author

Blyzniuk, Mykola ; Kazymyra, Irena

Author_Institution

CAD Dept., Lviv Polytech. Nat. Univ., Ukraine

fYear

2001

fDate

2001

Firstpage

375

Lastpage

383

Abstract

The development of special software tool named FIESTA (Faults Identification and Estimation of Test Ability) for the defect/fault analysis in the complex gates from industrial cell library is considered. This software tool is destined for the test developers and IC designers and is aimed at: a) probabilistic-based analysis of CMOS physical defects in VLSI circuits: b) facilitation of the work on development of hierarchical probabilistic automatic generation of test patterns; c) improvement of the layout in order to decrease the influence of spot defects on IC manufacturability. We consider the principle concepts of the FIESTA development. They are based on the developed approaches to 1) the identification and estimation of the probability of actual faulty functions resulting from shorts and opens caused by spot defects in the conductive layers of IC layout, and to 2) the evaluation of the effectiveness/usefulness of the test vector components in faults detection

Keywords

CMOS digital integrated circuits; VLSI; automatic test pattern generation; cellular arrays; circuit layout CAD; design for manufacture; design for testability; fault diagnosis; integrated circuit layout; integrated circuit testing; CMOS VLSI circuit; FIESTA software tool; IC design; IC layout; complex gates; conductive layers; defect analysis; design for manufacturability; design for testability; fault analysis; hierarchical probabilistic automatic test pattern generation; probabilistic analysis; spot defects; standard cell library; Automatic testing; CMOS integrated circuits; Circuit faults; Circuit testing; Computer industry; Fault diagnosis; Integrated circuit layout; Integrated circuit testing; Software testing; Software tools;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

Conference_Location

San Francisco, CA

ISSN

1550-5774

Print_ISBN

0-7695-1203-8

Type

conf

DOI

10.1109/DFTVS.2001.966791

Filename

966791