Title :
Design of a totally self checking signature analysis checker for finite state machines
Author :
Ottavi, M. ; Cardarilli, G.C. ; Cellitti, D. ; Pontarelli, S. ; Re, M. ; Salsano, A.
Author_Institution :
Dept. of Electron. Eng., Rome Univ., Italy
Abstract :
This paper describes the design of a totally self-checking signature analysis checker to be used to implement self-checking finite state machines. The application of the signature analysis method is studied taking into account trade off criteria concerning area and timing constraints requested in specific applications. In this paper, we propose a novel VHDL realization of this methodology suitable for the implementation of the SSMM for satellite applications. Finally, we present a general criterion to evaluate the optimal solution in terms of area overhead between the proposed method and a typical duplication and compare strategy
Keywords :
automatic test equipment; built-in self test; design for testability; fault tolerant computing; finite state machines; hardware description languages; high level synthesis; logic testing; semiconductor storage; VHDL; area overhead; complexity; criterion; optimal solution; self-checking finite state machines; self-checking signature analysis checker; solid state mass memory; Automata; Circuit faults; Design automation; Design engineering; Digital systems; Fault tolerant systems; Hardware design languages; Logic; Satellites; Timing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-1203-8
DOI :
10.1109/DFTVS.2001.966794
