An automatic design for flash memory testing

Due to the easy implementation and high fault coverage, the march-like algorithms have been used for the flash memory testing. However, the testing complexity of the flash memory testing is mainly dominated by the memory address spaces. Many tremendous human efforts are required to design a built-in self-test test pattern generator for a large capacity of flash memory. To save the design overhead, an automatic design for any size of flash memory testing has been proposed in this paper. By using the Microsoft Visual Basic (VB) programming tool, a graphical user interface (GUI) has been designed for the user to apply the specification of flash memory. Then the test pattern generator of the embedded march-like algorithms for testing the flash memory has been designed automatically and converted to the hardware description language (HDL) file. Under the control of the VB, without any manual labor, the HDL file can be compiled and simulated by the Altera FPGA tool - Quartus II and converted to the specific files for applying the Data Generator Instruments to generate the test signals.