DocumentCode :
1918741
Title :
Modeling of signal integrity in bus communications with timed data flow SystemC-AMS
Author :
Wang, Ruomin ; Denoulet, Julien ; Feruglio, Sylvain ; Vallette, Farouk ; Garda, Patrick
Author_Institution :
Univ. Pierre et Marie Curie, Paris 06, UPMC, UMR 7606, Laboratoire d´Informatique de Paris 6, F-75005
fYear :
2013
fDate :
24-26 Sept. 2013
Firstpage :
1
Lastpage :
6
Abstract :
The paper presents a new method for modeling the functionality and Signal Integrity (SI) performances of bus communications at a high level of abstraction. Using neural networks, we build a SystemC/SystemC-AMS virtual platform that combines functional modules, which represent the operative behavior of the system, and non-functional modules based on neural network approximation, which display the systems SI characteristics. Our method was demonstrated by modeling a Universal Serial Bus 3.0 (USB 3.0) system and was applied to the prediction of transient waveforms and eye diagrams. Compared to a HSPICE simulation, our method achieves excellent accuracy (mean absolute error of 1%) with a much shorter simulation time (×6000 speedup).
Keywords :
Accuracy; Integrated circuit modeling; Mathematical model; Neural networks; Silicon; Training; Universal Serial Bus; High-level modeling; Signal Integrity; SystemC/SystemC-AMS; USB 3.0 Bus Communication; neural networks;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Specification & Design Languages (FDL), 2013 Forum on
Conference_Location :
Paris, France
ISSN :
1636-9874
Type :
conf
Filename :
6646634
Link To Document :
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