Multi-Gigabit communication: the ADC bottleneck1

The economies of scale in modern communication systems are enabled by architectures that take advantage of Moore´s law to implement most transceiver functionalities in digital signal processing (DSP). The bottleneck in scaling such ldquomostly digitalrdquo architectures to multi-Gigabit rates becomes the analog-to-digital converter (ADC): high-speed, high-precision ADCs are either not available, or are too costly and power-hungry. In this paper, we report on recent results on two approaches towards addressing this bottleneck. The first is to simply use drastically low-precision (1-4 bit) ADCs than current practice. This could be suitable for applications that require limited dynamic range (e.g., line-of-sight communication using small constellations), but there are fundamental and algorithmic questions as to whether all the functions of a communication receiver can be realized with such a significant nonlinearity early in the processing. The second is to use a time-interleaved ADC, where a large number of low-speed, high-precision ADCs are employed in parallel to realize a high-speed, high-precision ADC. This is more generally applicable to applications requiring large dynamic range (e.g., large constellations and/or dispersive channels), but the important question is how to effectively address the mismatch between the component ADCs, which leads to a performance floor if left uncompensated.