DocumentCode
1920206
Title
EP120: A 0.35um, 3V/5V, Mixed-Signal/RF BiCMOS Technology
Author
Doyle, D. ; Moloney, K. ; O´Sullivan, A. ; Smith, Y. ; Waldron, N. ; Deignan, A. ; Tuthill, M. ; O´Neill, M.
Author_Institution
Analog Devices B.V., Limerick, Ireland
fYear
2000
fDate
11-13 Sept. 2000
Firstpage
580
Lastpage
583
Abstract
This paper describes a 0.35um BiCMOS process, the key aspect of which is the range of applications served by the process. To service the varied requirements, the process is designed to support high yielding, high performance active devices, high precision, well-matched passive elements, plus a variety of options such as thick metal, high-Q inductors. The process is also compatible with an existing dualvoltage CMOS process. The paper describes some novel features such as the NPN collector design, process thermal sequence and presents results from all the devices and a PLL circuit.
Keywords
Annealing; BiCMOS integrated circuits; CMOS process; CMOS technology; Capacitors; Implants; Isolation technology; Radio frequency; Silicon carbide;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference, 2000. Proceeding of the 30th European
Conference_Location
Cork, Ireland
Print_ISBN
2-86332-248-6
Type
conf
DOI
10.1109/ESSDERC.2000.194844
Filename
1503774
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