P1–2: A novel poly-Si TFTs with vacuum cavity next to the gate-oxide edge

Poly-Si TFTs with vacuum cavity next to the gate-oxide edge (quasi T-gate TFTs) have been fabricated with the wet-etching of gate-oxide and in-situ vacuum encapsulation techniques. The device characteristics of the quasi T-gate TFTs are examined and better than those of conventional TFTs, resulting from the vacuum cavity as the offset region to reduce the leakage current and as the field-induced drain (FID) to maintain the on-current. Furthermore, owing to the simultaneous reduction of the vertical and lateral electric field near the drain as bias stressing, the quasi T-gate TFTs achieve superior reliability than conventional ones.