Title :
Layout Optimalisation for Bipolar Power Transistors
Author :
Mouthaan, A.J. ; Scheer, A. B v d ; Boezen, HJ ; Krabbenborg, B. ; de Graaff, H.C.
Author_Institution :
MESA Research Institute, University of Twente, PO Box 217, 7500 AE Enschede, The Netherlands; University of Twente
Abstract :
The layout of bipolar power devices for e.g. (audio) amplifier applications has to be such that for a given chip-area the maximum amount of power can be dissipated. High dissipation can be a result of a large Vce, large Ic or a combination of both. It is known that thermal and electrical instabilities can occur in localised areas of the transistor, limiting the overall capabilities of the structure [1]. To optimise the layout a full 3D simulation of the device is necessary including surrounding silicon. Lumped circuit modelling [2] has been applied here to determine the overall thermal resistance for different layouts; the lower the thermal resistance for a certain area, the better the layout.
Keywords :
Circuit simulation; Coupling circuits; Fingers; Power amplifiers; Power transistors; Resistance heating; Temperature dependence; Thermal conductivity; Thermal resistance; Voltage;
Conference_Titel :
Solid State Device Research Conference, 1995. ESSDERC '95. Proceedings of the 25th European
Conference_Location :
The Hague, The Netherlands
