Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST)

Author

Nassif-Khalil, Sameh G. ; Salama, C. Andre T

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

fYear

2002

fDate

2002

Firstpage

81

Lastpage

84

Abstract

This paper reports on a novel Super Junction LDMOST in SOS technology (SJ-LDMOST) targeting Power Integrated Circuits (PICs) and discusses a CMOS compatible process used in the implementation of the device. The proposed structure uses a simple and practical method to achieve charge compensation between the n and p SJ-pillars and a uniform electric field distribution in the forward blocking mode. 3D device simulations indicate that a significant reduction of the specific on-resistance for a given breakdown voltage can be achieved over conventional RESURF devices using a realistic aspect ratio for the SJ pillars.

Keywords

CMOS integrated circuits; compensation; integrated circuit modelling; integrated circuit reliability; power MOSFET; power integrated circuits; semiconductor device breakdown; silicon-on-insulator; 3D device simulations; CMOS compatible process; SJ-LDMOST; SOS; Si; Silicon-On-Sapphire Technology; Super Junction LDMOST; aspect ratio; breakdown voltage; charge compensation; forward blocking mode; power integrated circuits; specific on-resistance; uniform electric field distribution; CMOS process; CMOS technology; Circuit simulation; Conductivity; Doping; Electric breakdown; MOSFETs; Mirrors; Region 2; Strontium;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2002. Proceedings of the 14th International Symposium on

Print_ISBN

0-7803-7318-9

Type

conf

DOI

10.1109/ISPSD.2002.1016176

Filename

1016176