Enhanced FPGA based three level space vector pulse width modulation with active neutral point balancing

This paper presents an FPGA based implementation of an improved space vector pulse width modulation for neutral point clamped three-level topologies. For this purpose the flatspace modulation calculating the timings is used in combination with an optimized switching pattern to reduce the switching edges to a minimum. Additionally a combination of two methods for balancing the neutral point is developed which are both implemented without adding any additional harmonics to the modulated output.