DocumentCode
1925922
Title
Robust 80 V LDMOS and 100 V DECMOS in a streamlined SOI technology for analog power applications
Author
Merchant, Steven ; Efland, Taylor ; Haynie, Sheldon ; Headen, William ; Kajiyama, Kengo ; Paiva, Scott ; Shaw, Robert ; Tachikake, Isao ; Tani, Toshiyuki ; Tsai, Chin-Yu
Author_Institution
Silicon Technol. Dev., Texas Instrum., Manchester, NH, USA
fYear
2002
fDate
2002
Firstpage
185
Lastpage
188
Abstract
A new 80 V SOI process is described with best in class LDMOS performance. The use of standard SOI material, deep trench isolation, a simplified process flow, and a well defined component set make this technology well suited for telecom, industrial, and automotive applications.
Keywords
MOS analogue integrated circuits; automotive electronics; isolation technology; power integrated circuits; silicon-on-insulator; 100 V; 80 V; DECMOS; LDMOS; Si; analog power applications; automotive applications; deep trench isolation; industrial applications; process flow; streamlined SOI technology; telecom applications; well defined component set; Copper; Costs; Etching; Immune system; Implants; Instruments; Isolation technology; Robustness; Telecommunications; Thermal resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs, 2002. Proceedings of the 14th International Symposium on
Print_ISBN
0-7803-7318-9
Type
conf
DOI
10.1109/ISPSD.2002.1016202
Filename
1016202
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