DocumentCode :
1927585
Title :
SSM-MP: more scalability in shared-memory multi-processor
Author :
Iwasa, Shigeaki ; Shing, Shung Ho ; Mogi, Hisashi ; Nozuwe, Hiroshi ; Hayashi, Hiroo ; Wakamori, Osamu ; Ohmizo, Takashi ; Tanaka, Kuninori ; Sakai, Hiroshi ; Saito, Mitsuo
Author_Institution :
Inf. & Commun. Syst. Lab., Toshiba Corp., Tokyo, Japan
fYear :
1995
fDate :
2-4 Oct 1995
Firstpage :
558
Lastpage :
563
Abstract :
Bus-based shared-memory multi-processors (SM-MP) have successfully been used commercially, since implementation requires no drastic changes to the programming paradigm. In this paper we propose the memory structure called SSM-MP (Scalable shared-memory multi-processors), aimed to shorten the cache refill latency and to relax the bus bottle neck problem. In this machine, main memory consists of local memories dedicated to each of the processors and something called MTag. MTag is a small piece of hardware that filters out bus traffic headed to the system bus and maintains cache coherency. A popular UNIX (SVR4 ES/MP) was ported. Original OS code works well due to its natural locality. Furthermore, by allocating tasks to the local memory, we were able to reduce the system bus traffic to nearly a quarter. SSM-MP is an effective approach in building a multi-processor system with a medium number (4-32) of processors
Keywords :
memory architecture; shared memory systems; MTag; SSM-MP; bus bottle neck problem; cache coherency; cache refill latency; multi-processor system; scalability; shared-memory multi-processor; Bandwidth; Delay; Filters; Hardware; Laboratories; Memory management; Neck; Programming profession; Scalability; System buses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-8186-7165-3
Type :
conf
DOI :
10.1109/ICCD.1995.528923
Filename :
528923
Link To Document :
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