Combined Partial Test Vector Reuse and FDR Coding for Two Dimensional SoC Test Compression

This paper proposes a novel approach to core based SoC test compression. Research works show that almost all the test vectors have the same part in common. Therefore there exists such a vector, from which parts of each test vector from the different test sets can be sought. Based on this, first we attempt to find a vector named overlapped vector which contains parts of each test vector and has shorter length than that of the sum of each test vector´s length. Second the overlapped test vectors are further compressed utilizing frequency-directed run-length (FDR) coding. Due to the fact that the test application time is proportional to the length of test vector, our proposal achieves as short test time as possible. Experimental results demonstrate that the proposed method obtains reduced test application time and significant test data compression rate.