Stacked Capacitor in Trench Cell for 16M-DRAM

A 16 Mbit DRAM cell based on a Stacked Capacitor (STC) in an isolated trench has been investigated. The storage node of the capacitor consists of an As doped poly Si spacer in Trench. The poly Si spacer is connected to source of the transfer gate by a buried trench contact. Thie ``STC in trench´´ cell allows trench to trench/active area distances of 0.7¿m. The ONO dielectric (deff = 9 nm) on the As doped poly Si spacer exhibits similar properties as ONO on Si substrate. Using the reported ``STC in trench´´ process a 5.12 ¿m!² DRAM cell (design rules: 0.7¿m) has been fabricated.