Title :
A 10 Gb/s ATM data synchroniser
Author :
Wong, T.Y.K. ; Sitch, J. ; McGarry, S.
Author_Institution :
BNR, Ottawa, Ont., Canada
fDate :
Oct. 29 1995-Nov. 1 1995
Abstract :
A data synchroniser based on an analog controlled data delay driven by a clock to data phase detector is reported. The synchroniser is fabricated in an HBT processes and runs at 10 Gb/s with 200 ps delay range.
Keywords :
asynchronous transfer mode; bipolar digital integrated circuits; data communication equipment; digital communication; synchronisation; timing circuits; 10 Gbit/s; 200 ps; ATM data synchroniser; HBT process; analog controlled data delay; clock to data phase detector; digital phase detector; Asynchronous transfer mode; Clocks; Delay; Detectors; Error correction; Frequency synchronization; Heterojunction bipolar transistors; Jitter; Phase detection; Switches;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1995. Technical Digest 1995., 17th Annual IEEE
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-2966-X
DOI :
10.1109/GAAS.1995.528959
