A Three-micron Pitch, Three Layer Metallization and Dielectric Scheme with Application to a One Micron CMOS Process

An interlayer dielectric scheme and three layer metal process which has been implemented as part of a one micron CMOS process for ASIC products is described. The interlayer dielectric scheme is outlined with particular reference to step coverage and planarisation issues. The advantages of the use of Anti-Reflective Coatings (ARC) to improve control at contact and metal prints are described. Good control of the etched features has also been achieved. The process has been proven by its implementation in a one micron CMOS process schedule which has yielded working circuitry of high complexity, including a 38K SRAM cell.