Thermal stress analysis of FCBGA during cooling under reflow process

Thermal stresses in Flip Chip Ball Grid Array (FCBGA) generated by the Chip Package Interaction (CPI) while cooling during the reflow process were calculated using Finite Element Analysis (FEA). This paper is focused on the thermal stresses in Cu/low-k on-chip interconnect where the non-uniform temperature distribution is considered. The temperature distribution was first calculated by FEA using the boundary conditions which were detemined by the measured temperatrue profiles. Significant temperature non-uniformity were simulated in packaging substrate due to its low thermal conductivity. Under this non-uniform temperature distribution in pagkaging substrate, the accuracy of thermal stress simulation results is improved to 10-15% and the die size dependency of thermal stress which was not obtained by the uniform temperature condition is successfully simulated.