Title :
A 440 MHz 16 bit counter in CMOS standard cells
Author :
Hoppe, B. ; Kroh, Chr ; Meuth, H. ; Stöhr, M.
Author_Institution :
Fachhochschule Darmstadt, Germany
Abstract :
We present a high speed counter architecture, which operates in 0.7 μm CMOS standard cells at a measured clock rate of 440 MHz. The basic architecture provides the following key features: (a) the speed performance is essentially limited only by the delay of a single flip-flop; (b) the counter state stabilizes to the actual state within a single clock cycle
Keywords :
CMOS logic circuits; application specific integrated circuits; counting circuits; flip-flops; high-speed integrated circuits; 0.7 micron; 16 bit; 440 MHz; CMOS standard cells; counter state stabilization; flip-flop delay; high speed counter architecture; speed performance; Array signal processing; CMOS process; CMOS technology; Clocks; Counting circuits; Delay; Frequency; Logic; Signal design; Signal processing;
Conference_Titel :
ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-4980-6
DOI :
10.1109/ASIC.1998.722966
