TCAD Analysis of a Vertical RF Power Transistor

A detailed TCAD analysis of a low-C_gd high-power RF MOSFET incorporating a 0.25 mum sidewall gate is presented. A novel conductive plate is placed in the vicinity of the gate poly as well as underneath the gate interconnects to provide a complete shield of the gate from the influence of drain potential. The fabricated vertical DMOS device exhibits a I_d(sat) = 750 muA/mum and an extrinsic transconductance g_m(sat) = 75 muS/mum under saturation, and a BVDSS = 110 V. The simulated I-V and C-V characteristics match very well with the measured data. TCAD sheds light on the bias dependence of the capacitances. The penetration of potential contours near the n-drift drain recess is identified as the cause for a sharp drop in output capacitance against V_ds.