Title :
An accurate soft error propagation analysis technique considering temporal masking disablement
Author :
Kimi, Yuta ; Matsukawa, Go ; Yoshida, Shuhei ; Izumi, Shintaro ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko
Author_Institution :
Grad. Sch. of Syst. Inf., Kobe Univ., Kobe, Japan
Abstract :
This paper presents an accurate soft error propagation analysis technique for processor SER evaluation. Especially, we focus on Single Event Upset (SEU) in flip-flop which is a main contributor of processor SER. SEUs in flip-flops propagate combinational circuits with temporal masking and logical masking effects. The temporal masking is disabled when the erroneous flip-flop is disabled. The proposed technique is able to evaluate temporal masking disablement by combined analysis of temporal and logical effects. Experimental result shows that the proposed technique reduces 49.87% inaccuracy in average compared with the technique ignoring temporal masking disablement when the enabled probability of the erroneous flip-flop is 0.1.
Keywords :
combinational circuits; flip-flops; microprocessor chips; radiation hardening (electronics); SEU; combinational circuits; flip-flops; logical masking effects; processor SER evaluation; single event upset; soft error propagation analysis technique; temporal masking disablement; Accuracy; Clocks; Error analysis; Flip-flops; Monte Carlo methods; Probability; logical masking; processor soft error rate; soft error propagation; temporal masking;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2015 IEEE 21st International
Conference_Location :
Halkidiki
DOI :
10.1109/IOLTS.2015.7229822