DocumentCode
1947876
Title
A 250MHz-2GHz wide range delay-locked loop
Author
Kim, Byung-Guk ; Kim, Lee-Sup
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea
fYear
2004
fDate
3-6 Oct. 2004
Firstpage
139
Lastpage
142
Abstract
This paper describes a wide range delay-locked loop (DLL) for synchronous clocking, to support dynamic frequency and voltage scaling. The DLL achieves a wide range by using multiple phases from its variable delay line. A phase detector is proposed to increase the locking speed and alleviate the phase offset owing to the inherent mismatch of the charge pump. The DLL achieves a static phase error of under 10 ps. At 1 GHz, its RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps respectively.
Keywords
UHF circuits; delay lines; delay lock loops; phase detectors; timing jitter; 1 GHz; 250 MHz to 2 GHz; DLL; analog type DLL; charge pump mismatch; dynamic frequency scaling; dynamic voltage scaling; locking speed; multiple phase variable delay line; peak-to-peak jitter; phase detector; phase error; phase offset; synchronous clocking; wide range delay-locked loop; Clocks; Delay lines; Detectors; Dynamic voltage scaling; Frequency synchronization; Jitter; Logic; Phase detection; Phase locked loops; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN
0-7803-8495-4
Type
conf
DOI
10.1109/CICC.2004.1358758
Filename
1358758
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